The FP6806 asserts a reset signal whenever the VDD supply voltage declines below the preset threshold and monitors the system voltages from 0.4V to 5V. A time delayed reset can be accomplished with an additional external capacitor. The FP6806 quiescent current is very low and suitable for portable and battery-operated applications.
The output RST (RST) signal is set to be active low. RST (RST) remains low for the delay time after reset condition is deasserted and then goes high. The FP6806 provides ± 1% threshold accuracy.
FP6806 is available in space-saving TSOT-23-3, TSOT-23-5, TSOT-23-6 packages.